Spread-spectrum clocking is a technique used to reduce the radiated emissions (also known as EMI (Electromagnetic Interference) or RFI (Radio Frequency Interference)) from clocked systems such as microprocessors or I/O links. The concept is shown in FIGS. 1 and 2. Fclk, the nominal clock frequency, is the average rate at which data can be processed or transmitted. The EMI spectrum from a system employing a fixed-rate clock is roughly approximated by the sharp peaks centered at multiples of Fclk in FIG. 2. When the clock frequency is varied over time as shown in FIG. 1, the peaks in FIG. 2 tend to spread out. Although the total energy in each harmonic is unchanged, the peaks are reduced because the energy is spread out over a wider range of frequencies. FIG. 1 shows frequency vs. time for the common choice of triangle-wave modulation.
FIG. 3 shows an example of a prior art spread-spectrum clock generation circuit 300. As shown, the circuit 300 employs a phase frequency detector (PFD) 302, a charge pump 304, a loop filter 306, an adder 308, a voltage-controlled oscillator (VCO) 310, and a feedback divider 312. Without the adder 308, the circuit 300 corresponds to a conventional charge-pump phase-locked loop (PLL). The feedback divider 312 forces the output clock frequency to an integer multiple of the reference clock frequency. The PFD 302 compares the phases of the reference clock and the output of the feedback divider, and outputs a signal proportional to the difference. If the phase of the output of the feedback divider 312 lags the phase of the reference clock, voltage pulses indicative of the phase difference are output from the PFD 302 on a first output 314a. Conversely, if the phase of the output of the feedback divider 312 leads the phase of the reference clock signal, voltage pulses indicative of the phase difference are output from the PFD 302 on a second output 314b. The first and second outputs 314 are coupled to the charge pump 304, which converts the voltage pulses from the PFD 302 into current pulses. The current pulses generated by the charge pump 304 are, in turn, integrated by the loop filter 306. A modulating signal 316 added at the input of the VCO 310 causes the output clock frequency to vary over time with the same period as the modulating signal.
The amplitude and shape of the output clock frequency profile approximately follows the modulating signal, but is subject to several non-idealities. First, the constant of proportionality between the modulating (voltage) signal and the output clock frequency is determined by the VCO gain Kvco, which is subject to process, supply voltage, and temperature (PVT) variation. Second, the feedback loop attenuates frequency components of the modulating signal within the PLL loop bandwidth. VCO noise suppression or settling time requirements often make it impractical to limit the PLL bandwidth enough to avoid significant distortion of the modulating signal. Pre-emphasis of the modulating signal can reduce this effect, but is difficult to implement and can never provide perfect cancellation due to PVT variation and device mismatch.
PLL-based spread-spectrum clock generation also suffers from other limitations. For example, it is difficult to program modulation parameters or change the basic modulation shape of an analog waveform. Automated testing of a spread-spectrum clock generated by such a system is also difficult because it requires detection and processing of a large number of closely-spaced clock edges.
One technique for digital clock synthesis is disclosed in U.S. Pat. No. 6,909,311 (“the '311 patent”), issued Jun. 21, 2005 and entitled “Method and apparatus for synthesizing a clock signal,” which is incorporated herein by reference in its entirety. One of the digital clock synthesis circuits disclosed in the '311 patent is shown in FIG. 4 herein. As shown, the circuit 400 comprises a clock generating circuit 402, a multiplexing circuit 404, and a clock synthesizing circuit 406. The clock generating circuit 402 comprises a delay-locked loop (DLL) that generates sixty-four delayed versions of a reference clock, the multiplexing circuit 404 comprises two 64-to-1 multiplexers 405a, 405b, and the clock synthesizing circuit 406 comprises a 2-to-1 multiplexer 408 and a flip-flop 410.
FIG. 5 is a graph illustrating clock phases output from the DLL of FIG. 4. As shown, the delayed clocks output by the DLL may be evenly spaced in time, so that the difference in delay between DLL[i] and DLL[i+1] is one sixty-fourth of the reference clock period.
Assuming the synthesized clock is initially low, the 2-to-1 multiplexer 408 selects the output of the “R” multiplexer 405a. A rising edge of the clock selected by the “R” multiplexer 405a causes the flip-flop 410 to toggle and the 2-to-1 multiplexer 408 now selects the output of the “F” multiplexer 405b. A rising edge on the clock selected by the “F” multiplexer 405b causes the flip-flop 410 to toggle again, returning to the initial state. This method allows the synthesis of a clock with arbitrary (within one sixty-fourth of the reference clock period) placement of the rising and falling edge, as determined by the selected taps of the multiplexers 405a-b. FIG. 6 shows the circuit of FIG. 4 along with resulting waveforms at particular nodes when the rising edge location is set to tap “8” and the falling edge location is set to tap “28.”